linux-hardening - Re: [PATCH 3/7] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent

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Date: Mon, 12 Feb 2024 14:33:10 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
 James Schulman <james.schulman@...rus.com>,
 David Rhodes <david.rhodes@...rus.com>,
 Richard Fitzgerald <rf@...nsource.cirrus.com>,
 Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>,
 Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Ricardo Rivera-Matos <rriveram@...nsource.cirrus.com>,
 Bjorn Andersson <andersson@...nel.org>, Abel Vesa <abel.vesa@...aro.org>,
 Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
 Kees Cook <keescook@...omium.org>, Tony Luck <tony.luck@...el.com>,
 "Guilherme G. Piccoli" <gpiccoli@...lia.com>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
 alsa-devel@...a-project.org, patches@...nsource.cirrus.com,
 linux-sound@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 linux-hardening@...r.kernel.org
Subject: Re: [PATCH 3/7] arm64: dts: qcom: sm8550: Mark QUPs and GPI
 dma-coherent

On 12/02/2024 14:10, Konrad Dybcio wrote:
> These peripherals are DMA-coherent on 8550. Mark them as such.
> 
> Interestingly enough, the I2C master hubs are not.

Yeah they are not DMA capable at all

> 
> Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index b8f1c7f97e48..d696ec6c6850 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -812,6 +812,7 @@ gpi_dma2: dma-controller@...000 {
>   			dma-channels = <12>;
>   			dma-channel-mask = <0x3e>;
>   			iommus = <&apps_smmu 0x436 0>;
> +			dma-coherent;
>   			status = "disabled";
>   		};
>   
> @@ -823,6 +824,7 @@ qupv3_id_1: geniqup@...000 {
>   			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
>   				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
>   			iommus = <&apps_smmu 0x423 0>;
> +			dma-coherent;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
>   			status = "disabled";
> @@ -1322,6 +1324,7 @@ gpi_dma1: dma-controller@...000 {
>   			dma-channels = <12>;
>   			dma-channel-mask = <0x1e>;
>   			iommus = <&apps_smmu 0xb6 0>;
> +			dma-coherent;
>   			status = "disabled";
>   		};
>   
> @@ -1335,6 +1338,7 @@ qupv3_id_0: geniqup@...000 {
>   			iommus = <&apps_smmu 0xa3 0>;
>   			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
>   			interconnect-names = "qup-core";
> +			dma-coherent;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
>   			status = "disabled";
>

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>